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1. general description the PTN3300A is a high-speed level shifter device which converts four lanes of low-swing ac-coupled differential input signals to dvi and hdmi compliant open-drain current-steering differential output signals, up to 2.25 gbit/s per lane. each of these lanes provides a level-shifting differential buffer to translate from low-swing ac-coupled differential signaling on the source side, to tmds-type dc-coupled differential current-mode signaling terminated into 50 w to 3.3 v on the sink side. additionally, the PTN3300A provides a single-ended active inverting buffer for voltage translation of the hpd signal from 5 v on the sink side to 1.1 v on the source side and provides a channel for level shifting of the ddc channel (consisting of a clock and a data line) between 3.3 v source-side and 5 v sink-side. the ddc channel is implemented using pass gate technology allowing level shifting as well as disablement (isolation between source and sink) of the clock and data lines. the low-swing ac-coupled differential input signals to the PTN3300A typically come from a display source with multi-mode i/o, which supports multiple display standards, e.g., displayport, hdmi and dvi. while the input differential signals are con?gured to carry dvi or hdmi coded data, they do not comply with the electrical requirements of the dvi v1.0 speci?cation or hdmi v1.3a speci?cation. by using PTN3300A, chip set vendors are able to implement such recon?gurable i/os on multi-mode display source devices, allowing the support of multiple display standards while keeping the number of chip set i/o pins low. see figure 1 . the PTN3300A main high-speed differential lanes feature low-swing self-biasing differential inputs which are compliant to the electrical speci?cations of displayport standard v1.1 and/or pci express standard v1.1 , and open-drain current-steering differential outputs compliant to dvi v1.0 and hdmi v1.3a electrical speci?cations. the PTN3300A also supports power-saving modes in order to minimize current consumption when no display is active or connected. the PTN3300A supports level translation functions and features supporting dvi and hdmi. it is identical to the ptn3300b except that the hpd_source_n output is the logic inverse function of input hpd_sink, level shifted to 1.1 v. for a fully-featured hdmi/dvi level shifter function that supports active buffering of the ddc lines and hdmi dongle detect, the ptn3301 should be used. PTN3300A is powered from a single 3.3 v power supply consuming a small amount of power (120 mw typ.) and is offered in two different 48-terminal hwqfn packages, one laminate based (no terminals visible from edge of the package), and one leadframe-based (terminals visible from edge of the package). PTN3300A dvi/hdmi level shifter with inverting 1.1 v hpd rev. 01 30 june 2008 product data sheet
PTN3300A_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 30 june 2008 2 of 23 nxp semiconductors PTN3300A dvi/hdmi level shifter with inverting 1.1 v hpd remark: tmds clock and data lanes can be assigned arbitrarily and interchangeably to d[4:1]. fig 1. typical application system diagram 002aad645 out_d1 - out_d1+ in_d1 - in_d1+ hpd_source_n hpd_sink scl_sink sda_sink ddc_en (0 v to 3.3 v) scl_source sda_source out_d2 - out_d2+ in_d2 - in_d2+ out_d3 - out_d3+ in_d3 - in_d3+ out_d4 - out_d4+ in_d4 - in_d4+ PTN3300A oe_n dvi connector 5 v 5 v 0 v to 5 v 0 v to 1.1 v 3.3 v 3.3 v 3.3 v ac-coupled differential pair clock clock lane data lane data lane data lane ac-coupled differential pair tmds data ac-coupled differential pair tmds data ac-coupled differential pair tmds data tx tx ff tmds clock pattern multi-mode display source tx tx ff tmds coded data tx tx ff tmds coded data tx tx ff tmds coded data pcie phy electrical configuration ddc i/o (i 2 c-bus) pcie output buffer reconfigurable i/os pcie output buffer pcie output buffer pcie output buffer
PTN3300A_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 30 june 2008 3 of 23 nxp semiconductors PTN3300A dvi/hdmi level shifter with inverting 1.1 v hpd 2. features 2.1 high-speed tmds level shifting n converts four lanes of low-swing ac-coupled differential input signals to dvi and hdmi compliant open-drain current-steering differential output signals n tmds level shifting operation up to 2.25 gbit/s per lane (225 mhz character clock) n integrated 50 w termination resistors for self-biasing differential inputs n back-current safe outputs to disallow current when device power is off and monitor is on n disable feature to turn off tmds inputs and outputs and to enter low-power state 2.2 ddc level shifting n integrated ddc level shifting (3.3 v source to 5 v sink side) n 0 hz to 400 khz clock frequency n back-power safe to disallow backdrive current when power is off or when ddc is not enabled 2.3 hpd level shifting n hpd inverting level shift from 0 v on the sink side to 1.1 v on the source side, or from 5 v on the sink side to 0 v on the source side n integrated 200 k w pull-down resistor on hpd sink input guarantees input low when no display is plugged in 2.4 general n power supply 3.3 v 10 % n esd resilience to 3.5 kv hbm, 1 kv cdm n power-saving modes by source-side disablement (using output enable) as well as sink-side detection (using hpd) n back-current-safe design on all sink-side terminals n transparent operation: no re-timing or software con?guration required 3. ordering information table 1. ordering information type number package name description version PTN3300Ahf hwqfn48r plastic thermal enhanced very very thin quad ?at package; no leads; 48 terminals; resin based; body 7 7 0.7 mm sot1031-2 PTN3300Ahf2 hwqfn48 plastic thermal enhanced very very thin quad ?at package; no leads; 48 terminals; body 7 7 0.65 mm sot1074-1
PTN3300A_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 30 june 2008 4 of 23 nxp semiconductors PTN3300A dvi/hdmi level shifter with inverting 1.1 v hpd 4. functional diagram fig 2. functional diagram of PTN3300A 002aad646 out_d1 - out_d1+ input bias 50 w 50 w in_d1 - in_d1+ hpd level shifter hpd_source_n (0 v to 1.1 v) hpd_sink (0 v to 5 v) 200 k w scl_sink sda_sink ddc_en (0 v to 3.3 v) scl_source sda_source out_d2 - out_d2+ in_d2 - in_d2+ out_d3 - out_d3+ in_d3 - in_d3+ out_d4 - out_d4+ in_d4 - in_d4+ PTN3300A oe_n enable enable enable enable input bias 50 w 50 w input bias 50 w 50 w input bias 50 w 50 w enable enable enable enable ddc level shifter
PTN3300A_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 30 june 2008 5 of 23 nxp semiconductors PTN3300A dvi/hdmi level shifter with inverting 1.1 v hpd 5. pinning information 5.1 pinning hwqfn48r package supply ground is connected to both gnd pins and exposed center pad. gnd pins must be connected to supply ground for proper device operation. for enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the pcb in the thermal pad region. fig 3. pin con?guration for hwqfn48r out_d4+ out_d4 - v dd out_d3+ out_d3 - gnd out_d2+ out_d2 - v dd out_d1+ out_d1 - gnd v dd gnd n.c. scl_source sda_source hpd_source_n rext gnd n.c. n.c. v dd gnd in_d4+ in_d4 - v dd in_d3+ in_d3 - gnd in_d2+ in_d2 - v dd in_d1+ in_d1 - gnd 002aad647 oe_n v dd gnd scl_sink sda_sink hpd_sink gnd ddc_en v dd n.c. n.c. gnd PTN3300Ahf 12 25 11 26 10 27 9 28 8 29 7 30 6 31 5 32 4 33 3 34 2 35 136 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 terminal 1 index area transparent top view
PTN3300A_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 30 june 2008 6 of 23 nxp semiconductors PTN3300A dvi/hdmi level shifter with inverting 1.1 v hpd hwqfn48 package supply ground is connected to both gnd pins and exposed center pad. gnd pins must be connected to supply ground for proper device operation. for enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the pcb in the thermal pad region. fig 4. pin con?guration for hwqfn48 in_d4+ in_d4 - v dd in_d3+ in_d3 - gnd in_d2+ in_d2 - v dd in_d1+ in_d1 - gnd oe_n v dd gnd scl_sink sda_sink hpd_sink gnd ddc_en v dd n.c. n.c. gnd out_d4+ out_d4 - v dd out_d3+ out_d3 - gnd out_d2+ out_d2 - v dd out_d1+ out_d1 - gnd v dd gnd n.c. scl_source sda_source hpd_source_n rext gnd n.c. n.c. v dd gnd 002aad648 PTN3300Ahf2 transparent top view 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 8 9 10 11 12 7 6 5 4 1 3 2 terminal 1 index area
PTN3300A_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 30 june 2008 7 of 23 nxp semiconductors PTN3300A dvi/hdmi level shifter with inverting 1.1 v hpd 5.2 pin description table 2. pin description symbol pin type description oe_n, in_dx and out_dx signals oe_n 25 3.3 v low-voltage cmos single-ended input output enable and power saving function for high-speed differential level shifter path. when oe_n = high: in_dx termination = high-impedance out_dx outputs = high-impedance; zero output current when oe_n = low: in_dx termination = 50 w out_dx outputs = active in_d4+ 48 self-biasing differential input low-swing differential input from display source with pci express electrical signalling. in_d4+ makes a differential pair with in_d4 - . the input to this pin must be ac coupled externally. in_d4 - 47 self-biasing differential input low-swing differential input from display source with pci express electrical signalling. in_d4 - makes a differential pair with in_d4+. the input to this pin must be ac coupled externally. in_d3+ 45 self-biasing differential input low-swing differential input from display source with pci express electrical signalling. in_d3+ makes a differential pair with in_d3 - . the input to this pin must be ac coupled externally. in_d3 - 44 self-biasing differential input low-swing differential input from display source with pci express electrical signalling. in_d3 - makes a differential pair with in_d3+. the input to this pin must be ac coupled externally. in_d2+ 42 self-biasing differential input low-swing differential input from display source with pci express electrical signalling. in_d2+ makes a differential pair with in_d2 - . the input to this pin must be ac coupled externally. in_d2 - 41 self-biasing differential input low-swing differential input from display source with pci express electrical signalling. in_d2 - makes a differential pair with in_d2+. the input to this pin must be ac coupled externally. in_d1+ 39 self-biasing differential input low-swing differential input from display source with pci express electrical signalling. in_d1+ makes a differential pair with in_d1 - . the input to this pin must be ac coupled externally. in_d1 - 38 self-biasing differential input low-swing differential input from display source with pci express electrical signalling. in_d1 - makes a differential pair with in_d1+. the input to this pin must be ac coupled externally. out_d4+ 13 tmds differential output dvi and hdmi compliant tmds output. out_d4+ makes a differential pair with out_d4 - . out_d4+ is in phase with in_d4+. out_d4 - 14 tmds differential output dvi and hdmi compliant tmds output. out_d4 - makes a differential pair with out_d4+. out_d4 - is in phase with in_d4 - . out_d3+ 16 tmds differential output dvi and hdmi compliant tmds output. out_d3+ makes a differential pair with out_d3 - . out_d3+ is in phase with in_d3+. out_d3 - 17 tmds differential output dvi and hdmi compliant tmds output. out_d3 - makes a differential pair with out_d3+. out_d3 - is in phase with in_d3 - . out_d2+ 19 tmds differential output dvi and hdmi compliant tmds output. out_d2+ makes a differential pair with out_d2 - . out_d2+ is in phase with in_d2+. out_d2 - 20 tmds differential output dvi and hdmi compliant tmds output. out_d2 - makes a differential pair with out_d2+. out_d2 - is in phase with in_d2 - .
PTN3300A_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 30 june 2008 8 of 23 nxp semiconductors PTN3300A dvi/hdmi level shifter with inverting 1.1 v hpd [1] hwqfn48r and hwqfn48 package supply ground is connected to both gnd pins and exposed center pad. gnd pins must be connected to supply ground for proper device operation. for enhanced thermal, electrical, and board level performance, the expo sed pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the pcb in the thermal pad region. out_d1+ 22 tmds differential output dvi and hdmi compliant tmds output. out_d1+ makes a differential pair with out_d1 - . out_d1+ is in phase with in_d1+. out_d1 - 23 tmds differential output dvi and hdmi compliant tmds output. out_d1 - makes a differential pair with out_d1+. out_d1 - is in phase with in_d1 - . hpd and ddc signals hpd_sink 30 5 v cmos single-ended input 0 v to 5 v (nominal) input signal. this signal comes from the dvi or hdmi sink. a high value indicates that the dvi or hdmi sink is connected; a low value indicates that the sink is disconnected. hpd_sink is pulled down by an integrated 200 k w pull-down resistor. a low input level on this pin will automatically put the PTN3300A in standby mode for lowest power consumption. hpd_source_ n 7 1.1 v cmos single-ended output 0 v to 1.1 v (nominal) output signal. this is the level-shifted logic-inverted version of the hpd_sink signal. scl_source 9 single-ended 3.3 v ddc i/o pass gate 3.3 v source-side ddc clock i/o. pulled up by external termination to 3.3 v. sda_source 8 single-ended 3.3 v ddc i/o pass gate 3.3 v source-side ddc data i/o. pulled up by external termination to 3.3 v. scl_sink 28 single-ended 5 v ddc i/o pass gate 5 v sink-side ddc clock i/o. pulled up by external termination to 5 v. sda_sink 29 single-ended 5 v ddc i/o pass gate 5 v sink-side ddc data i/o. pulled up by external termination to 5 v. ddc_en 32 3.3 v cmos input enables the ddc level shifter path. when ddc_en = low, ddc level shifter is disabled. when ddc_en = high, ddc level shifter are enabled. note that hpd_sink needs to be high for the ddc channel to be enabled. supply and ground v dd 2, 11, 15, 21, 26, 33, 40, 46 3.3 v dc supply supply voltage; 3.3 v 10 %. gnd [1] 1, 5, 12, 18, 24, 27, 31, 36, 37, 43 ground supply ground. all ground pins must be connected to ground for proper operation. feature control signals rext 6 analog i/o current sense port used to provide an accurate current reference for the differential outputs out_dx. for best output voltage swing accuracy, use of a 10 k w resistor (1 % tolerance) from this terminal to gnd is recommended. may also be left open-circuit or tied to either v dd or gnd. miscellaneous n.c. 3, 4, 10, 34, 35 no connection to the die not connected. may be left open-circuit or tied to gnd or v dd either directly or via a resistor. table 2. pin description continued symbol pin type description
PTN3300A_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 30 june 2008 9 of 23 nxp semiconductors PTN3300A dvi/hdmi level shifter with inverting 1.1 v hpd 6. functional description refer to figure 2 functional diag r am of PTN3300A . the PTN3300A level shifts four lanes of low-swing ac-coupled differential input signals to dvi or hdmi compliant open-drain current-steering differential output signals, up to 2.25 gbit/s per lane. it has integrated 50 w termination resistors for ac-coupled differential input signals. an enable signal oe_n can be used to turn off the tmds inputs and outputs, thereby minimizing power consumption. the tmds outputs are back-power safe to disallow current ?ow from a powered sink while the PTN3300A is unpowered. the PTN3300A's ddc level-shifter allows 3.3 v source-side termination and 5 v sink-side termination. the PTN3300A offers the back-power safe feature to disallow backdrive current from the ddc clock and data lines when power is off or when ddc is not enabled. an enable signal dcc_en enables the level shifter block. the PTN3300A also provides voltage translation for the hot plug detect (hpd) signal from 0 v/5 v on the sink side, inverting and level-shifting to 1.1 v/0 v on the source side. PTN3300A also automatically goes into low power mode when the sink is not connected (hpd_sink is low). the PTN3300A does not re-time any data. it contains no state machines. no inputs or outputs of the device are latched or clocked. because the PTN3300A acts as a transparent level shifter, no reset is required. 6.1 flexible and power-ef?cient enable and disable features PTN3300A offers different ways to enable or disable functionality, using the output enable (oe_n), hot plug detect (hpd_sink) and ddc enable (ddc_en) inputs. whenever the PTN3300A is disabled using hpd_sink or oe_n, the device will be in standby mode and power consumption will be minimal; otherwise the PTN3300A will be in active mode and power consumption will be nominal. these three inputs each affect the operation of PTN3300A differently: oe_n affects only the tmds channels, ddc_en affects only the ddc channel, and hpd_sink affects both tmds and ddc channels. the following sections and truth table describe their detailed operation. 6.1.1 hot plug detect with power-saving feature the hpd channel of PTN3300A in fact has a dual function: as a level-shifting inverting buffer to pass the hpd logic signal from the display sink device (via input hpd_sink) on to the display source device (via output hpd_source_n), as well as a detection input for determining when the PTN3300A will go into standby mode to save power consumption. the PTN3300A will automatically disable both the tmds and ddc channels when the hpd input indicates that no display is connected (indicated by hpd_sink = low), upon which power consumption is minimized. the power-down behavior in hpd power-saving mode is identical to the active disablement using both the oe_n input and the ddc_en input. the logic state of the hpd_source_n output always follows the inverse logic state of the hpd_sink input, regardless of whether the device is in active or standby mode.
PTN3300A_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 30 june 2008 10 of 23 nxp semiconductors PTN3300A dvi/hdmi level shifter with inverting 1.1 v hpd 6.1.2 output enable function (oe_n) when input oe_n is asserted (active low), the in_dx and out_dx signals are fully functional provided that hpd_sink input is high. input termination resistors are enabled and the internal bias circuits are turned on. when oe_n is de-asserted (inactive high), the out_dx outputs are in a high-impedance state and drive zero output current. the in_dx input buffers are disabled and in_dx termination is disabled. internal bias circuits for the differential inputs and outputs are turned off. power consumption is minimized. remark: note that oe_n has no in?uence on the hpd_sink input, hpd_source_n output, or the scl and sda level shifters. oe_n only affects the high-speed tmds channel. 6.1.3 ddc channel enable function (ddc_en) the ddc_en pin is active high and can be used to isolate a badly behaved slave. when ddc_en is low, the ddc channel is turned off. the ddc_en input should never change state during an i 2 c-bus operation. note that disabling ddc_en during a bus operation will hang the bus, while enabling ddc_en during bus traf?c would corrupt the i 2 c-bus operation. hence, ddc_en should only be toggled while the bus is idle. (see i 2 c-bus speci?cation). 6.1.4 enable/disable truth table [1] a low level on input hpd_sink disables both the tmds and ddc channels. [2] a high level on input oe_n disables only the tmds channels. [3] a low level on input ddc_en disables only the ddc channel. [4] out_dx channels enabled means outputs out_dx toggling in accordance with in_dx differential input voltage switching. [5] ddc channel enabled means sda_sink is connected to sda_source and scl_sink is connected to scl_source. [6] the hpd_source_n output logic state follows the inverse of the hpd_sink input logic state regardless of active or standby mo de. table 3. hpd_sink, oe_n and ddc_en enabling and power saving functions truth table inputs channels mode hpd_sink [1] oe_n [2] ddc_en [3] in_dx out_dx [4] ddc [5] hpd_source_n [6] low x x high-impedance high-impedance; zero output current high-impedance high standby high low low 50 w termination to v rx(bias) enabled high-impedance low active high low high 50 w termination to v rx(bias) enabled enabled low active high high low high-impedance high-impedance; zero output current high-impedance low standby high high high high-impedance high-impedance; zero output current enabled low standby with ddc channel enabled
PTN3300A_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 30 june 2008 11 of 23 nxp semiconductors PTN3300A dvi/hdmi level shifter with inverting 1.1 v hpd 6.2 analog current reference the rext pin (pin 6) is an analog current sense port used to provide an accurate current reference for the differential outputs out_dx. for best output voltage swing accuracy, use of a 10 k w resistor (1 % tolerance) connected between this terminal and gnd is recommended. if an external 10 k w 1 % resistor is not used, this pin can be left open-circuit, or connected to gnd or v dd , either directly (0 w ) or using pull-up or pull-down resistors of value less than 10 k w . in any of these cases, the output will function normally but at reduced accuracy over voltage and temperature of the following parameters: output levels (v ol ), differential output voltage swing, and rise and fall time accuracy. 6.3 backdrive current protection the PTN3300A is designed for backdrive prevention on all sink-side terminals. this supports user scenarios where the display is connected and powered, but the PTN3300A is unpowered. in these cases, the PTN3300A will sink no more than a negligible amount of leakage current, and will block the display (sink) termination network from driving the power supply of the PTN3300A or that of the inactive dvi or hdmi source.
PTN3300A_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 30 june 2008 12 of 23 nxp semiconductors PTN3300A dvi/hdmi level shifter with inverting 1.1 v hpd 7. limiting values [1] human body model: ansi/eos/esd-s5.1-1994, standard for esd sensitivity testing, human body model - component level; electrostatic discharge association, rome, ny, usa. [2] charged device model: ansi/eos/esd-s5.3-1-1999, standard for esd sensitivity testing, charged device model - component level; electrostatic discharge association, rome, ny, usa. 8. recommended operating conditions [1] input signals to these pins must be ac-coupled. [2] operation without external reference resistor is possible but will result in reduced output voltage swing accuracy. for details, see section 6.2 . 8.1 current consumption table 4. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v dd supply voltage - 0.3 +4.6 v v i input voltage 3.3 v cmos inputs - 0.3 v dd + 0.5 v 5.0 v cmos inputs - 0.3 6.0 v t stg storage temperature - 65 +150 c v esd electrostatic discharge voltage hbm [1] - 3500 v cdm [2] - 1000 v table 5. recommended operating conditions symbol parameter conditions min typ max unit v dd supply voltage 3.0 3.3 3.6 v v i input voltage 3.3 v cmos inputs 0 - 3.6 v 5.0 v cmos inputs 0 - 5.5 v v i(av) average input voltage dc value at in_dn+, in_dn - inputs [1] -0 - v r ref(ext) external reference resistance [2] connected between rext pin (pin 6) and gnd; 1% -10 - k w t amb ambient temperature operating in free air - 40 - +85 c table 6. current consumption symbol parameter conditions min typ max unit i dd supply current oe_n = 0 and hpd_sink = 1; active mode 10 35 50 ma oe_n = 1 or hpd_sink = 0; standby mode -550 m a
PTN3300A_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 30 june 2008 13 of 23 nxp semiconductors PTN3300A dvi/hdmi level shifter with inverting 1.1 v hpd 9. characteristics 9.1 differential inputs [1] ui (unit interval) = t bit (bit time). [2] ui is determined by the display mode. nominal bit rate ranges from 250 mbit/s to 2.25 gbit/s per lane. nominal ui at 2.25 gbit/s = 444 ps. 400 ps = 444 ps - 10 %. [3] v rx_diffp-p = 2 | v rx_d+ - v rx_d - | . applies to in_dx signals. [4] v i(cm)m(ac) = | v rx_d+ +v rx_d - | /2 - v rx(cm) . v rx(cm) = dc (avg) of | v rx_d+ +v rx_d - | /2. [5] intended to limit power-up stress on source side pcie output buffers. [6] differential inputs will switch to a high-impedance state when oe_n is low. table 7. differential input characteristics for in_dx signals symbol parameter conditions min typ max unit ui unit interval [1] [2] 400 - 4000 ps v rx_diffp-p differential input peak-to-peak voltage [3] 0.175 - 1.200 v t rx_eye receiver eye time minimum eye width at in_dx input pair 0.8 - - ui v i(cm)m(ac) peak common-mode input voltage (ac) includes all frequencies above 30 khz [4] - - 100 mv z rx_dc dc input impedance 40 50 60 w v rx(bias) bias receiver voltage voltage at in_dx when in_dx = open circuit [5] 1.0 1.2 1.4 v z i(se) single-ended input impedance inputs in high-impedance state [6] 100 - - k w
PTN3300A_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 30 june 2008 14 of 23 nxp semiconductors PTN3300A dvi/hdmi level shifter with inverting 1.1 v hpd 9.2 differential outputs the level shifters differential outputs are designed to meet dvi version 1.0 and hdmi v1.3a speci?cations. [1] v tt is the dc termination voltage in the dvi or hdmi sink. v tt is nominally 3.3 v. termination resistance is nominally 50 w . [2] the open-drain output pulls down from v tt . [3] swing down from tmds termination voltage (3.3 v 10 %). [4] maximum rise/fall time at 2.25 gbit/s = 444 ps. 400 ps = 444 ps - 15 %. [5] this differential skew budget is in addition to the skew presented between in_d+ and in_d - paired input pins. [6] this lane-to-lane skew budget is in addition to skew between differential input pairs. [7] jitter budget for differential signals as they pass through the level shifter. 7.4 ps = 0.02 ui at 1.65 gbit/s. table 8. differential output characteristics for out_dx signals symbol parameter conditions min typ max unit v oh(se) single-ended high-level output voltage [1] v tt - 0.01 v tt v tt + 0.01 v v ol(se) single-ended low-level output voltage [2] v tt - 0.60 v tt - 0.50 v tt - 0.40 v d v o(se) single-ended output voltage variation logic 1 and logic 0 state applied respectively to differential inputs in_dn; r ref(ext) connected. see t ab le 5 [3] 450 500 600 mv i oz off-state output current single-ended - - 10 m a t r rise time 20 % to 80 % [4] 75 - 180 ps t f fall time 80 % to 20 % [4] 75 - 180 ps t sk skew time intra-pair [5] --10ps inter-pair [6] - - 250 ps t jit jitter time jitter contribution [7] - - 7.4 ps
PTN3300A_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 30 june 2008 15 of 23 nxp semiconductors PTN3300A dvi/hdmi level shifter with inverting 1.1 v hpd 9.3 hpd_sink input, hpd_source_n output [1] low-speed input changes state on cable plug/unplug. [2] measured with hpd_sink at v ih maximum and v il minimum. [3] time from hpd_sink changing state to hpd_source_n changing state. includes hpd_source_n rise/fall time. [4] time required to transition from v oh to v ol or from v ol to v oh . [5] guarantees hpd_sink is low when no display is plugged in. 9.4 oe_n and ddc_en inputs [1] measured with input at v ih maximum and v il minimum. 9.5 ddc characteristics table 9. hpd characteristics symbol parameter conditions min typ max unit v ih high-level input voltage hpd_sink [1] 2.0 5.0 5.3 v v il low-level input voltage hpd_sink 0 - 0.8 v i li input leakage current hpd_sink [2] --10 m a v oh high-level output voltage hpd_source_n; i oh = 100 m a; hpd_sink = low 0.7 - 1.1 v v ol low-level output voltage hpd_source_n; i ol = 100 m a; hpd_sink = high 0 - 0.2 v t pd propagation delay from hpd_sink to hpd_source_n; 50 % to 50 %; c l =10pf [3] - - 200 ns t t transition time hpd_source_n rise/fall; 10%to90%; c l =10pf [4] 1 - 20 ns r pd pull-down resistance hpd_sink input pull-down resistor [5] 100 200 300 k w table 10. oe_n and ddc_en input characteristics symbol parameter conditions min typ max unit v ih high-level input voltage 2.0 - - v v il low-level input voltage - - 0.8 v i li input leakage current oe_n pin [1] --10 m a table 11. ddc characteristics symbol parameter conditions min typ max unit f clk clock frequency scl_source, sda_source, scl_sink, sda_sink - - 400 khz on state (ddc_en = high and hpd_sink = high) r on on resistance pass gate in on state; i o = 15 ma; v o = 0.4 v - 7 30 w v o(sw) switch output voltage source side; v i = 3.3 v; i o = - 100 m a 1.8 2.1 2.4 v sink side; v i = 5.0 v; i o = - 100 m a 1.8 2.1 2.4 v c io input/output capacitance v i = 3.3 v; i o = - 100 m a-510pf off state (ddc_en = low) i li input leakage current source side; 0 v < v i < 3.3 v - 1- +1 m a sink side; 0 v < v i < 5.0 v - 1- +1 m a c io input/output capacitance v i = 3.3 v; i o = - 100 m a-15pf
PTN3300A_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 30 june 2008 16 of 23 nxp semiconductors PTN3300A dvi/hdmi level shifter with inverting 1.1 v hpd 10. package outline fig 5. package outline sot1031-2 (hwqfn48r) references outline version european projection issue date iec jedec jeita sot1031-2 - - - - - - - - - sot1031-2 08-03-06 08-03-26 unit mm max nom min 0.80 0.70 0.65 0.27 0.25 0.23 5.35 5.25 5.15 7.1 7.0 6.9 5.35 5.25 5.15 0.5 5.5 0.42 0.40 0.38 0.1 a dimensions (mm are the original dimensions) hwqfn48r: plastic thermal enhanced very very thin quad flat package; no leads 48 terminals; resin based; body 7 x 7 x 0.7 mm b d 7.1 7.0 6.9 d h e e h e e 1 5.5 e 2 l l 1 0.10 0.05 0.00 v w 0.05 y 0.05 y 1 0.1 0 2.5 5 mm scale detail x a terminal 1 index area b a d e c y 1 x c y terminal 1 index area b e 2 e 1 e e 1/2 e 1/2 e a c b v m c w m d h e h l l 1 36 13 24 25 48 37 1 12
PTN3300A_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 30 june 2008 17 of 23 nxp semiconductors PTN3300A dvi/hdmi level shifter with inverting 1.1 v hpd fig 6. package outline sot1074-1 (hwqfn48) references outline version european projection issue date iec jedec jeita sot1074-1 - - - - - - - - - sot1074-1 note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. unit mm max nom min 0.80 0.65 0.60 0.05 0.02 0.00 0.2 7.1 7.0 6.9 5.40 5.25 5.10 7.1 7.0 6.9 0.5 5.5 0.5 0.4 0.3 0.1 a (1) dimensions (mm are the original dimensions) hwqfn48: plastic thermal enhanced very very thin quad flat package; no leads; 48 terminals; body 7 x 7 x 0.65 mm 0 2.5 5 mm scale a 1 b 0.30 0.21 0.18 c d (1) d h e (1) e h 5.40 5.25 5.10 e e 1 e 2 5.5 l v 0.1 w 0.05 y 0.05 y 1 c y c y 1 x b a terminal 1 index area d e detail x c a a 1 b e 2 e 1 e e 1/2 e 1/2 e a c b v m c w m terminal 1 index area l e h d h 48 37 36 25 24 13 12 1 08-03-06 08-03-14
PTN3300A_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 30 june 2008 18 of 23 nxp semiconductors PTN3300A dvi/hdmi level shifter with inverting 1.1 v hpd 11. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 surface mount re?ow soldering description . 11.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electrical circuits. the soldered joint provides both the mechanical and the electrical connection. there is no single soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for ?ne pitch smds. re?ow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 11.2 wave and re?ow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. the re?ow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature pro?le. leaded packages, packages with solder balls, and leadless packages are all re?ow solderable. key characteristics in both wave and re?ow soldering are: ? board speci?cations, including the board ?nish, solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivity level of the packages ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering 11.3 wave soldering key characteristics in wave soldering are: ? process issues, such as application of adhesive and ?ux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath speci?cations, including temperature and impurities
PTN3300A_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 30 june 2008 19 of 23 nxp semiconductors PTN3300A dvi/hdmi level shifter with inverting 1.1 v hpd 11.4 re?ow soldering key characteristics in re?ow soldering are: ? lead-free versus snpb soldering; note that a lead-free re?ow process usually leads to higher minimum peak temperatures (see figure 7 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? re?ow temperature pro?le; this pro?le includes preheat, re?ow (in which the board is heated to the peak temperature) and cooling down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classi?ed in accordance with t ab le 12 and 13 moisture sensitivity precautions, as indicated on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during re?ow soldering, see figure 7 . table 12. snpb eutectic process (from j-std-020c) package thickness (mm) package re?ow temperature ( c) volume (mm 3 ) < 350 3 350 < 2.5 235 220 3 2.5 220 220 table 13. lead-free process (from j-std-020c) package thickness (mm) package re?ow temperature ( c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245
PTN3300A_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 30 june 2008 20 of 23 nxp semiconductors PTN3300A dvi/hdmi level shifter with inverting 1.1 v hpd for further information on temperature pro?les, refer to application note an10365 surface mount re?ow soldering description . 12. abbreviations msl: moisture sensitivity level fig 7. temperature pro?les for large and small components 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature table 14. abbreviations acronym description cdm charged-device model cec consumer electronics control ddc data display channel dvi digital visual interface emi electromagnetic interference esd electrostatic discharge hbm human body model hdmi high-de?nition multimedia interface hpd hot plug detect i 2 c-bus inter-integrated circuit bus i/o input/output nmos negative-channel metal-oxide semiconductor tmds transition minimized differential signaling vesa video electronics standards association
PTN3300A_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 30 june 2008 21 of 23 nxp semiconductors PTN3300A dvi/hdmi level shifter with inverting 1.1 v hpd 13. revision history table 15. revision history document id release date data sheet status change notice supersedes PTN3300A_1 20080630 product data sheet - -
PTN3300A_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 30 june 2008 22 of 23 nxp semiconductors PTN3300A dvi/hdmi level shifter with inverting 1.1 v hpd 14. legal information 14.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term short data sheet is explained in section de?nitions. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple dev ices. the latest product status information is available on the internet at url http://www .nxp .com . 14.2 de?nitions draft the document is a draft version only. the content is still under internal review and subject to formal approval, which may result in modi?cations or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. short data sheet a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request via the local nxp semiconductors sales of?ce. in case of any inconsistency or con?ict with the short data sheet, the full data sheet shall prevail. 14.3 disclaimers general information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. right to make changes nxp semiconductors reserves the right to make changes to information published in this document, including without limitation speci?cations and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use nxp semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customers own risk. applications applications that are described herein for any of these products are for illustrative purposes only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. limiting values stress above one or more limiting values (as de?ned in the absolute maximum ratings system of iec 60134) may cause permanent damage to the device. limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the characteristics sections of this document is not implied. exposure to limiting values for extended periods may affect device reliability. terms and conditions of sale nxp semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www .nxp .com/pro? le/ter ms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by nxp semiconductors. in case of any inconsistency or con?ict between information in this document and such terms and conditions, the latter will prevail. no offer to sell or license nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 14.4 trademarks notice: all referenced brands, product names, service names and trademarks are the property of their respective owners. 15. contact information for more information, please visit: http://www .nxp.com for sales of?ce addresses, please send an email to: salesad dresses@nxp.com document status [1] [2] product status [3] de?nition objective [short] data sheet development this document contains data from the objective speci?cation for product development. preliminary [short] data sheet quali?cation this document contains data from the preliminary speci?cation. product [short] data sheet production this document contains the product speci?cation.
nxp semiconductors PTN3300A dvi/hdmi level shifter with inverting 1.1 v hpd ? nxp b.v. 2008. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com date of release: 30 june 2008 document identifier: PTN3300A_1 please be aware that important notices concerning this document and the product(s) described herein, have been included in section legal information. 16. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 high-speed tmds level shifting . . . . . . . . . . . . 3 2.2 ddc level shifting . . . . . . . . . . . . . . . . . . . . . . . 3 2.3 hpd level shifting . . . . . . . . . . . . . . . . . . . . . . . 3 2.4 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 ordering information . . . . . . . . . . . . . . . . . . . . . 3 4 functional diagram . . . . . . . . . . . . . . . . . . . . . . 4 5 pinning information . . . . . . . . . . . . . . . . . . . . . . 5 5.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7 6 functional description . . . . . . . . . . . . . . . . . . . 9 6.1 flexible and power-ef?cient enable and disable features. . . . . . . . . . . . . . . . . . . . . . . . . 9 6.1.1 hot plug detect with power-saving feature . . . . 9 6.1.2 output enable function (oe_n) . . . . . . . . . . . 10 6.1.3 ddc channel enable function (ddc_en). . . . 10 6.1.4 enable/disable truth table . . . . . . . . . . . . . . . . 10 6.2 analog current reference . . . . . . . . . . . . . . . . 11 6.3 backdrive current protection . . . . . . . . . . . . . . 11 7 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 12 8 recommended operating conditions. . . . . . . 12 8.1 current consumption . . . . . . . . . . . . . . . . . . . 12 9 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 13 9.1 differential inputs . . . . . . . . . . . . . . . . . . . . . . 13 9.2 differential outputs . . . . . . . . . . . . . . . . . . . . . 14 9.3 hpd_sink input, hpd_source_n output . 15 9.4 oe_n and ddc_en inputs. . . . . . . . . . . . . . . 15 9.5 ddc characteristics . . . . . . . . . . . . . . . . . . . . 15 10 package outline . . . . . . . . . . . . . . . . . . . . . . . . 16 11 soldering of smd packages . . . . . . . . . . . . . . 18 11.1 introduction to soldering . . . . . . . . . . . . . . . . . 18 11.2 wave and re?ow soldering . . . . . . . . . . . . . . . 18 11.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 18 11.4 re?ow soldering . . . . . . . . . . . . . . . . . . . . . . . 19 12 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 20 13 revision history . . . . . . . . . . . . . . . . . . . . . . . . 21 14 legal information. . . . . . . . . . . . . . . . . . . . . . . 22 14.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 22 14.2 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 14.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 14.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 15 contact information. . . . . . . . . . . . . . . . . . . . . 22 16 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

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